This invention relates generally to programmable memories, and more particularly the invention relates to programming circuitry operable at low electrical voltage levels.
In the programming of electrical memories such as PROMs and EEPROMs a programming voltage on the order of 20 volts is required. With PROM devices an external power source is utilized. However, the programming of EEPROMs is accomplished using the chip operating voltage, typically 5 volts, with a high-voltage generator circuit in the chip developing the requisite programming voltage. In programming mode operation, a selected word line is raised to the programming voltage level sequentially by using a charge pump. See Brahmbhatt, U.S. Pat. No. 4,442,481, for "Low Power Decoder Circuit", and Gupta, U.S. Pat. No. 4,511,811, for "Charge Pump for Providing Programming Voltage to the Word Lines in a Semiconductor Memory Array".
It has become desirable to operate EEPROM devices from a battery source. However, a V.sub.CC of only approximately 2.2 volts might be available from the battery source rather than having a V.sub.CC of 5 volts. Circuit operation is not inhibited using the lower V.sub.CC, but programming (charge pumping) of the EEPROM devices is impacted. In the devices in the Brahmbhatt and Gupta patents, supra, enhancement mode transistors are utilized and such transistors have threshold voltages of approximately 1.5 volts. Two such transistors are effectively connected in series in the V.sub.PP circuit path and thus require at least 3 volts for operation--well above the 2.2 volts available using a battery power source.